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1/11 AN1302 application note april 2002 1.0 application note overview the ste10/100a is a single chip ethernet solution for pci bus adapter applications. its design is optimized for high throughput, low cpu utilization and low cost. it is optional to program ste10/100a as a mac mode and bring out the mii interface with the external phy. this application note is divided into the following topics: gen- eral description, software programmers guide, optional mac mode and mii interface configuration, print cir- cuit board layout guidelines, nic (network interface card) application design schematics and bill of materials. this application note should be reviewed with the ste10/100a data sheet. 2.0 general description the ste10/100a is a high performance, low power, 3.3v pci fast ethernet controller with integrated physical layer interface for 10base-t and 100base-tx application. the system diagram is shown as below. the ste10/100a provides both half-duplex and full-duplex operation, as well as support for full-duplex flow con- trol. it provides long fifo buffers for transmission and receiving, and early interrupt mechanism to enhance per- formance. the ste10/100a also supports acpi and pci compliant power management functions. some key features are listed as follows: ? ieee802.3u 100 base-tx and ieee802.3 10base-t compliant ? support for ieee802.3x flow control ? ieee802.3u auto-negotiation support for 10 base-t and 100base-tx ? pci bus interface rev. 2.2 compliant ? support pc99 wake on lan ? provides two independent long fifos with 2k bytes each for transmission and receiving ? pre-fetch up to two transmit packets to minimize inter frame gap(ifg) to 0.96us ? retransmits collided packet without reload from host memory within 64 bytes. ste10/100a - pci 10/100 ethernet controller with integrated phy
2/11 AN1302 application note ? provides writable flash rom and eprom as boot rom with size up to 128kb ? provides pci to access boot rom by byte, word, or double word ? provides serial interface for read/write 93c46 eeprom 3.0 software programmers guide stmicroelectronics supplies the drivers for the ste10/100a nic for a wide variety of operating systems such as dos, win95/98/nt, unix, linux, vxworks, and others. the software programmers guide is designed to help in understanding how the drivers work and/ or aid in the customer software development for the ste10/100a pci faster ethernet controller with integrated phy. 3.1 initialization flow ste10/100a supports the auto-configuration of plug and play. it will be automatically configured when placed in any system which supports plug and play and configuration management routines. right after the system starts, plug and play will search for the nic. the driver will query the resident configuration manager to obtain all necessary configuration information such as base io and irq. the driver can obtain the base io location using methods inherent in the specific driver specification being written to (such as net.cfg files for odi and protocol.ini files for ndis drivers). then, reset the mac (through register csr0) and phy (through register xr0). reset mac is also called software reset - this ensures that all registers are initialized to their reset values even if a driver was previously run on the nic. if a media type is need to be set, then force the media type through register xr0, otherwise go directly to read eeprom, obtain the pre-assigned configuration resources, and set the physical address registers csr25 and 26. if multicast needs to be set, then go to register csr27 and 28 to set multicast address table. otherwise build the transmit and receive descriptors (register csr 3 and 4) and prepare the corresponding buffers. then install nics isr (interrupt service routine) functions, and finally enable nics interrupt (write enable bit to csr17) and open nic tx and rx functions (csr6). the flow of ini- tializing ste10/100a is shown as below:
AN1302 application note 3/11 search nic get base io address get irq value reset mac (csr0) reset phy (xr0) need to set media type? read eeprom from csr9 set physical address (csr25, 26) need to set multicast? (force media) program the media type to xr0 yes no a set multicast address table (csr27, 28) no yes
4/11 AN1302 application note 3.2 interrupt service routine the first thing to do in the interrupt service routine is to check the interrupt status (register csr5 and csr16) and confirm the interrupt. then, disable the interrupt (csr16) from the further interrupt while in the interrupt ser- vice routine. then check for a fatal error by looking at register csr5 bit13. if a fatal error occurs, check csr16 to determine what type of error, and then reset all the processes and end the interrupt service routine. if no fatal error occurs, then go ahead to check receive and transmit complete interrupt (csr5 bit6 and bit0). if one of the two bits is set, check the ownership bit in the descriptor. if the system owns the descriptor, then process the packet, otherwise, go to end of the interrupt service routine. before exiting the interrupt service routine, the in- terrupts must be re-enabled. for the tx and rx functions within the blocks of "process the transmit packet" and "process the receive packet" respectively, the ste10/100a provides an easy to use buffer architecture. as packets are received, they are stored sequentially in the 2 kbyte receive fifo. the driver need only perform a series of reads from a particular register to move the packet from the fifo into system memory. similarly, the driver needs to only perform a prepare transmit descriptor and buffer prepare receive descriptor and buffer a install nic isr function open nic interrupt enable tx & rx functions end
AN1302 application note 5/11 series of writes to the same register in order to transmit a packet. this simplified buffer architecture enables the driver to implement streamlined data transfer routines. the flow chart of the interrupt service routine is shown as below: driver isr check for fatal error jump to next interrupt chain yes reset every process a no check interrup t status no clear interrupt status and disable interrupt end
6/11 AN1302 application note a end check receive complete interrupt(csr5) chec k descriptor ownbit process the receive packet no yes check transmit complete interrupt(csr5) chec k descriptor ownbit yes process the transmit packet no no yes
AN1302 application note 7/11 4.0 mac mode and mii interface ste10/100a can be configured to operate in mac mode and use flash boot rom port as an mii port to control an external phy device. there are two methods that can be used to program the boot rom pins as mii interface pins and put ste10/100a in the mac mode. one method is from hardware configuration, the other is from soft- ware. ? to program the boot rom pins as mii interface pins from software, write 0x0024 to the test register "ctestr1" at address 0xfc. when ste10/100a is configured to run in the mac mode (boot rom pins programmed as mii interface pins), the multiplexed pins are defined as follows: pin 56 = bra0/mrxerr pin 68 = brd1/mrxd1 pin 57 = bra1/mcol pin 69 = brd2/mrxd2 pin 58 = bra2/mcrs pin 70 = brd3/mrxd3 pin 59 = bra3/mdio pin 71 = brd4/mrxdv pin 63 = bra6/mtxd0 pin 78 = broe#/txclk pin 64 = bra7/mtxd1 pin 79 = brwe#/rxclk pin 65 = bra8/mtxd2 pin 80 = bra10/mtxen pin 66 = bra9/mtxd3 pin 81 = bra11/mdc pin 67 = brd0/mrxd0 the register controlling the mdio pin of the ste10/100a is csr9 (offset = 0x48) and is implemented in the following manner: ? csr9[19]: mii mdio data in. used by ste10/100a to read mdio data from the phy. ? csr9[18]: mii mdio operation mode. when csr9[18]=1 the phy is in a read operation mode. when csr9[18]=0 the phy is in a write operation mode. ? csr9[17]: mii mdio data write. write mdio data to phy by writing 1 or 0 to this bit. ? csr9[16]: mii data clock is an output signal mdc to the phy. 5.0 pcb layout guidelines the goal of any complex mix-signal system design such as the one which includes both analog and digital func- tionality is to achieve the most robust system performance possible. performance aspects such as snr (signal to noise ratio), ber (bit-error-rate), emi, and general signal integrity must be considered. the right combination of component placement, signal trace routing practices, and power supply/grounding distribution are part of a robust and reliable system. this section gives the guidelines that should be considered during designing a 10/ 100 ethernet nic when employing ste10/100a in conjunction with the common magnetics and rj-45 connec- tor. 5.1 component placement guidelines regarding optimal component placement practices include: ? keep the distance between ste10/100a and the transformer, as well as the transformer and the rj-45 connector as short as possible.
8/11 AN1302 application note ? make sure the crystal device is close to ste10/100a pin x1 and x2, and stay away from the following items: ? tx+/-, rx+/- differential pairs. ? pcb edge. ? transformer. ? any other high frequency items and the associated traces. ? tx pull-up resistors, rx termination resistors and capacitors should be as close to ste10/100a as pos- sible. ? the ferrite beads and decoupling capacitors should be placed as close to ste10/100a as possible, and the traces should be short. 5.2 controlled impedance of signal traces it is important to incorporate controlled impedance routing for the signal traces which carry the 125mbps serial bit stream. standard micro-strip or strip-line techniques are recommended. it is important to choose an imped- ance of 50 for each trace that transports the 125mbps signals between the rj-45 connector and the transform- er, and between the transformer and ste10/100a. this is necessary in order to match the 100 differential impedance of the unshielded twisted pair cable. 5.3 signal trace routing some general guidelines regarding the optimal signal trace routing are listed as follows: ? minimal length controlled impedance signal traces to minimize reflections and decrease noise sensitiv- ities. ? matched length differential signal traces to minimize jitter. ? route trace corners at a radius >45 degrees. ? minimized number of vias for any one given signal trace minimizes radiation. ? all controlled impedance traces routed directly over or under uninterrupted power or ground planes on adjacent layer(s) as this minimizes coupled noise into signal lines. some specific guidelines regarding ste10/100a nic signal trace routing: tx and rx signal trace routing: ? avoid right angle on the signal traces. whenever necessary the round angle or 45 degree angle is rec- ommended. ? the trace width should be at least 2x the minimum unit of the layout program or wider than 8 mils. ? the length of the differential traces tx+ and tx- as well as rx+ and rx- should be equal and the total length of each signal trace should not be longer than 2cm. ? keep tx and rx traces within the same signal plane and do not use vias. ? the space between the differential traces tx+ and tx- as well as rx+ and rx- should be uniform and as close to each other as possible but not less than 8 mils. ? keep the distance between the tx and rx differential pairs as far as possible - separate the ground planes underneath tx and rx signal pairs to reduce the cross talk. ? keep the tx and rx traces away from the clock and power supply traces. ? whenever possible, always put ground planes around the tx and rx traces.
AN1302 application note 9/11 ? the digital signal traces should stay away from the analog signal and power supply traces. if impossible, traces should cross at 90 degrees with the analog signal and power supply routing at the other plane(s). ? power supply traces should be short and it is always suggested to route them in the format of a plane. ground should always be routed in the format of a plane. 6.0 nic schematics and bom stmicroelectronics has the ste10/100a demo board available, and the demo board is a pci bus nic card. the nic application design schematics can be found on the website at: http://www.st.com/stonline/prodpres/dedicate/connect/datacom/ste10/ste10.htm the corresponding bill of materials are as follows:
10/11 AN1302 application note bill of materials
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics a 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sin gapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com 11/11 an1141 application note 7.0 conclusion stmicroelectronics provides a complete solution with its ste10/100a chipset that comes with reference design hardware/software packages that allow manufacturers to quickly design easy and cost-effective applications. the design package includes: ? demo board (pci bus nic card) ? nic applications design schematics ? gerber files ? bill of materials ? detailed datasheet and documentation. the testing results show that ste10/100a has great performance and all the implemented functions meet or are better than the requirements specified by the ieee standard draft.

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